The inventive concept relates generally to electronic memory technologies, and more particularly to a high voltage switch and a nonvolatile memory device comprising the same.
Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM), and examples of nonvolatile memory devices include read only memory (ROM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and flash memory. Flash memory is an especially popular form of nonvolatile memory due to attractive features such as relatively high storage density, efficient performance, low cost per bit, and an ability to withstand physical shock.
A flash memory device typically requires a program and/or erase voltage that is higher than a power supply voltage VDD provided from an external source. The erase voltage is, for instance, 20V. To provide these or other high voltages, a high voltage Vpp is provided to a high voltage switch, which in turn provides a related high voltage to a memory cell array.
The high voltage switch operates according to a feedback structure of a depletion mode transistor and a positive metal oxide semiconductor (PMOS) transistor. The depletion mode transistor and PMOS transistor may have slightly different threshold voltages depending on process technology used to manufacture them. Where a threshold voltage of a depletion mode transistor is lower than an average value, an initial feedback loop start time of the high voltage switch is late. Where a threshold voltage of a depletion mode transistor is higher than an average value, a leakage current may occur in a PMOS transistor.
While the high voltage switch is turned on, a high voltage (e.g., 20V) continues to be maintained between a gate and a drain of a PMOS transistor. Thus, deterioration due to Fowler-Nordheim (FN) stress may occur in the PMOS transistor.